IP Integration Node

IP Integration Node 1.0

Free
It provides cycle accurate simulation within the LabVIEW execution environment

The LabVIEW FPGA IP Integration Node provides cycle accurate simulation within the LabVIEW execution environment for third party IP. In addition, the node provides a wizard interface that simply requires selecting VHDL files or a Xilinx Coregen® *.xco file. The node does not require creating wrapper code. The IP used in the IP Integration Node must use a single clock and must not have falling edge flip flops on the interface for correct co-simulation with the rest of the LabVIEW diagram.

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